Design and Implementation of Configurable SHIFT Instructions Targeted at Symmetrical Cipher Processing

High-performance and flexible configurable SHIFT instructions targeted at symmetrical cipher processing are proposed in this paper, in order to dispel the bottleneck of symmetrical cipher algorithms realized by universal processors. Through analyzing the processing characteristics and the structures of many symmetrical cipher algorithms, the proposed SHIFT instructions can support different processing data widths, different SHIFT modes. Furthermore, instruction level parallelism based on VLIW system structure and instruction inner parallelism by operating several sub word SHIFTs at the same time are designed too. Finally, corresponding reconfigurable hardware units to support the execution of each instruction forcefully is also exploited. For the characteristics of high efficiency and flexibility, the specific SHIFT instructions and the reconfigurable hardware processing units can be used as an ameliorative unit for processors to advance the performance in special processing for symmetrical cipher.