EFASBRAN: Error Free Adaptive Shared Buffer Router Architecture for Network on Chip

Router mainly used to control the data flow in Network on Chip (NoC). Every router can reliably control the traffic throughout the network. While controlling the heavy data inside the router, then the resultant may chance to get an error. Thus, to avoid an error inside the shared buffered router, a single bit error correction module externally added. Therefore, the main objective of this paper is to present an error-free low power and low latency shared buffered router architecture proposed for NoC. Thus, the improvements of proposed work as interpreted with respected to area, power and delay. Therefore, an entire experimental work simulated and synthesized by the Xilinx tool.