Synthesis of mealy FSM with multiple shared encoding of microinstructions and internal states

The method of hardware optimization of the logic circuit of finite state machine (FSM) with Mealy's outputs is proposed in this paper. Proposed method is based on the encoding identifiers, representing pairs (next state;microinstruction), for all suhtables of direct structural tahle of FSM. It leads to realization of FSM as s douhle-level structure with shared encoding of microinstructions and internal states, Identifiers are encoded hy a binary codps using Karnaugh maps. Special proposed method of assigning codes allows to divide this code into two subcodes for decoding microinstructions and internal states. These subcodes use only some variables required for encoding identifiers, but some variables are shared between these two subcodes. It leads to diminishing of number of variables required for encoding of identifiers and decoding of microinstructions or internal states. In this case any internal state is determined by the pair (current state, identifier sub code of internal state) and any microinstruction is determined by the similar pair (current state, identifier subcode of micro instruction) and then Mealy FSM can be implemented in proposed structure with multiple shared encoding of microinstructions and internal states (PAYs). Such approach permits to decma.'Ie the amount of required outputs of combinational part of FSM.