Model checking response times in Networked Automation Systems using jitter bounds

• Proposes methodology and workflow to verify Networked Automation Systems (NAS) timing performance during design, rather after deployment; thereby, eliminating the need for costly hardware upgrades and design modifications.
• A component based modelling approach for NAS capturing the timing performance, specifications and behaviour.
• The proposed method can be used study timing properties and guarantees in NAS.
• The proposed workflow can be used to benchmark different automation solutions and propose alternatives.
• The workflow is illustrated using experiments and industrial deployment example.

Response time (RT) of Networked Automation Systems (NAS) is affected by timing imperfections induced due to the network, computing and hardware components. Guaranteeing RT in the presence of such timing imperfections is essential for building dependable NAS, and to avoid costly upgrades after deployment in industries.This investigation proposes a methodology and work-flow that combines modelling, simulation, verification, experiments, and software tools to verify the RT of the NAS during the design, rather than after deployment. The RT evaluation work-flow has three phases: model building, modelling and verification. During the model building phase component reaction times are specified and their timing performance is measured by combining experiments with simulation. During the modelling phase, component based mathematical models that capture the network architecture and inter-connection are proposed. Composition of the component models gives the NAS model required for studying the RT performance on system level. Finally, in the verification step, the NAS formal models are abstracted as UPPAAL timed automata with their timing interfaces. To model timing interfaces, the action patterns, and their timing wrapper are proposed. The formal model of high level of abstraction is used to verify the total response time of the NAS where the reactions to be verified are specified using a subset of timed computation tree logic (TCTL) in UPPAAL model checker. The proposed approach is illustrated on an industrial steam boiler deployment.