کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
509389 | 865516 | 2009 | 9 صفحه PDF | دانلود رایگان |

This paper focuses on verification and validation of a model dedicated to mode handling of flexible manufacturing systems (FMSs). This model is specified using the synchronous formalism safe state machines (SSMs). The rigorous semantics that characterize such formalism enable to provide formal verification mechanisms ensuring determinism and dependability. A structured framework for verification and validation of the model dedicated to mode handling is proposed. The main properties being verified within this framework and the corresponding verification methods are presented. The approach is illustrated using an example of a manufacturing production cell. The formal analysis tools integrated into the development environment Esterel Studio are used within the design process.
Journal: Computers in Industry - Volume 60, Issue 2, February 2009, Pages 77–85