Study of hardware transactional memory characteristics and serialization policies on Haswell

• We evaluated the strengths and weaknesses of Intel extensions to HTM — TSX.
• We described features that are likely to yield performance gains when using TSX.
• We explored with the aid of a new tool called htm-pBuilder the performance of TSX.
• We introduced a efficient policy for guaranteeing forward progress on top of TSX.
• We explored various fall-back policy tunings and transaction properties of TSX.

This paper presents an extensive performance study of the implementation of Hardware Transactional Memory (HTM) in the Haswell generation of Intel x86 core processors. It evaluates the strengths and weaknesses of this new architecture by exploring several dimensions in the space of Transactional Memory (TM) application characteristics using the Eigenbench (Hong et al., 2010 [1]) and the CLOMP-TM (Schindewolf et al., 2012 [2]), benchmarks. This paper also introduces a new tool, called htm-pBuilder that tailors fallback policies and allows independent exploration of its parameters.This detailed performance study provides insights on the constraints imposed by the Intel’s Transaction Synchronization Extension (Intel’s TSX) and introduces a simple, but efficient policy for guaranteeing forward progress on top of the best-effort Intel’s HTM which was critical to achieving performance. The evaluation also shows that there are a number of potential improvements for designers of TM applications and software systems that use Intel’s TM and provides recommendations to extract maximum benefit from the current TM support available in Haswell.