Investigation into scaling I/O bound streaming applications productively with an all-FPGA cluster

The Reconfigurable Computing Cluster project is exploring novel parallel computing architectures in high performance computing with FPGA devices. Although there are no discrete microprocessors in the system, highly-integrated FPGAs (with embedded processors) are capable of hosting Linux-based systems and can run arbitrary MPI applications. This work present an investigation into accelerating I/O bound streaming applications through the coupling of custom computing cores, a hardware filesystem, and an integrated on-chip and off-chip network on the all-FPGA node cluster. Such an infrastructure enables productivity by minimizing hardware design while maintaining high performance. A hardware implementation of the BLASTn algorithm is used to demonstrate the performance gains and scalability of the custom computing cores across the Spirit cluster. Results show linear speedup across multiple nodes while supporting productivity by eliminating modifications to the original hardware core when scaling up to 512 parallel cores on the cluster.

► Linear scaling achieved with two network topologies (up to 32×) on 32 nodes.
► Up to 512 parallel BLAST hardware cores implemented.
► Successful integration with hardware filesystem and AIREN network.
► Minimal modifications required to original hardware core.
► Up to 57× speedup over single core AMD vs. single FPGA.