The relationship between the barrier–rib height of AC-PDP and address discharge characteristics

In order to drive high-image quality plasma display panels (PDP), the development of the fast scanning and addressing discharge is required. For image processing of 10 bits, the improvement of a dynamic false contour and driving high density PDP, the high-speed driving technology needs to be developed.In this study, the relationship between the barrier–rib height of the PDP and the address discharge for high-speed addressing were analyzed using a 4-in. stripe type VGA PDP panel. The barrier–rib height of the test panels varied between 100 and 180 μm. The results showed that the lower the barrier–rib was, the narrower the width of the scan pulse became. At a barrier–rib height of 100 μm, the minimum data voltage was 55.9 V and the dynamic margin of the address voltage was 23.5 V, with a scan pulse width of 0.8 μs and a ramp voltage of 220 V for a 4-in. test panel.