Sequential circuit design using quantum-dot cellular automata

Quantum-Dot Cellular Automata (QCA) as technology is a promising candidate that has tremendous potential to replace CMOS due to its outstanding features such as low-power, extremely high density, fast operation speed. This paper presents a comprehensive research for design of sequential circuits using QCA. The study comprehends portrayal of D-type FF device in QCA as an embedded binary wire. Distinctive constraints and requirements for timing of sequential circuits in QCA are explored. An algorithm based on stretching of paths that takes into account the topological sorted order of vertices of directed acyclic graph is presented for assigning proper clock zones and matching clock delays. The S27 circuit from the ISCAS89 sequential benchmark set is considered as case study for implementation in multilayer QCA using the proposed algorithm.