High speed and computationally efficient architecture for recursive interpolation filters

The paper presents high speed and computationally efficient architecture for the recursive interpolation filters for digital audio applications. Conversion of anti-imaging IIR filter that is an essential part of an interpolator, into an efficient interpolation filter is based on merged delay transformation. Any higher order filter is required to be implemented in parallel using first order and second order sections. This requirement provides the benefits of high speed processing. The optimal architectures for the first and second order sections are introduced. The computational cost is reduced up to 33.65% as compared to cascaded IIR-based interpolators and cost reduction of 89.48% is achieved as compared to polyphase FIR-based interpolators. A 1-to-4 interpolation filter is implemented on FPGA using Verilog HDL at input sampling frequency of 44.1 kHz and its power and critical path delay is compared with known architectures. Smaller critical path delay and lower computational cost are the important characteristics of this architecture which is highly desired in portable digital audio applications.