ESD Reliability Improvement of an HV nLDMOS by the Bulk FODs Engineering

The high voltage (HV) lateral double-diffused MOS (LDMOS) has a much lower on-resistance, a higher tolerance to breakdown voltage and a higher output power used for automotive ICs and high-frequency communication modules. However, its shortcomings are evident, including a high trigger voltage (Vt1), low holding voltage (Vh), low ESD discharge capability per unit length and multi-fingers unable to fully turn-on, which are serious impacted the ESD reliability capability. In this paper, the HV-nLDMOS device with adding field-oxide-devices (FODs) in the bulk area to make the trigger voltage effectively decreased, and in order to increase the ESD capability is investigated. Furthermore, the influence of bulk P+ area which was replaced by FODs in the bulk region on snapback parameters in a 0.25-μm 60-V high voltage process is evaluated. After that, the ESD capability has grate increased while the device with adding any FOD structures in the 0.25-μm 60-V high voltage process. The It2 value is > 7A and to be increased > 111.74% than that of a reference group. Noteworthy, this structure may make the trigger voltage (Vt1) too low to operate normally. Therefore, it should be careful considered that the problem of maximum FOD occupied ratio while using this methodology.