Error Threshold for Individual Faulty Gates Using Probabilistic Transfer Matrix (PTM)

In the progression from CMOS technology to nanotechnology, being able to assess reliability of nano-based electronic circuits is fast becoming necessary. Due to this phenomenon, several computational-based approaches have been proposed for the reliability assessment of nanotechnology-based circuit systems. In quantifying reliability measure of the desired circuit system, faulty gates are considered as the most active part of the system. To have reliable circuit system, apart from its faulty gates, the size of error, p, in those faulty gates has to be lesser than a threshold, ɛ*. In other words, for the individual faulty gates to function reliably, the parameter interval of error in those faulty gates has to be 0 ≤ p < ɛ*, based on their respective gate error thresholds. This hypothesized that reliability of the desired circuit system does not only depend on its faulty gates, but it also depends on the error threshold of those faulty gates above which no reliable computation is possible. Therefore, there is a need to compute the exact error thresholds for individual faulty gates above which no circuit made up using those gates can calculate reliably. This paper shows the employment of Probabilistic Transfer Matrix (PTM) model in deriving the exact error threshold for individual faulty gates. The employed methodology provides simple and powerful analytic method to analyze reliability measure of nanotechnology-based circuit systems.