Towards the hierarchical design of multilayer QCA logic circuit

As a potential alternative to CMOS technology, Quantum-dot Cellular Automata (QCA) promises efficient digital design with high device density and low power dissipation in the future. This work targets the development of multi-layered architecture in the QCA framework with the goal to build an efficient methodology for QCA based digital logic design. A strategy for modelling, digital devices around QCA multiplexer is framed, which directs to the conception of complex digital circuits with high device density and low latency (i.e., more quick functioning). The proposed multilayer design also points to inherent aspects of radius of effect of QCA cells and the layer spacing in multilayer architecture. Minimum clock zone (2 clock) with high compaction (0.01 μm2) is achieved for the multiplexer designed in QCA framework. A heuristic approach to synthesize multilayer synchronized QCA logic circuit is also proposed. Experimental results illustrate significant improvements in design level in terms of circuit area, cell count and clock over that of conventional design approaches.