کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
6879085 | 1443108 | 2018 | 5 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
DPL-based novel Binary-to-ternary converter on CMOS technology
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کلمات کلیدی
موضوعات مرتبط
مهندسی و علوم پایه
مهندسی کامپیوتر
شبکه های کامپیوتری و ارتباطات
پیش نمایش صفحه اول مقاله
چکیده انگلیسی
Encoding radix-2 data in radix-3 has the potential to allow faster computation with reduced power dissipation, reduced chip area and reduced interconnect overhead. Use of ternary encoding has the potential to minimize hot-spot generation and bring down fabrication costs due to reduced complexity. Efficient binary-to-ternary conversion is needed to attain these benefits in today's binary-dominated digital world. This paper presents a novel strategy to convert from a 2-valued binary input to a 3-valued ternary output. The proposed converter operates in 4 steps: (I) Synchronous complementary input generation, (II) Binary to unary conversion, (III) Unary to ternary interfacing, and (IV) Ternary output generation. A design using double pass-transistor logic delay equalized through coarse and fine-tuning is presented. Ternary values are encoded using 0, 0.9 and 1.8â¯V to represent ternary digit (trit) values of 0, 1 and 2. The proposed converter design has been validated using T-Spice transient-response simulation on TSMC 0.18â¯Âµm SPDM CMOS technology at 25â¯Â°C on Tanner EDA V.13. The worst-case response of the proposed design was identified using corner analysis with typical, slow and fast PVT variation.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: AEU - International Journal of Electronics and Communications - Volume 92, August 2018, Pages 69-73
Journal: AEU - International Journal of Electronics and Communications - Volume 92, August 2018, Pages 69-73
نویسندگان
Aloke Saha, Dipankar Pal,