A 12-bit 100 MS/s pipelined ADC without using front-end SHA

This paper presents a model and a novel architecture of a low-power pipelined analog-to-digital converter (ADC) without using front-end Sample and Hold Amplifier (SHA) stage. The modeling of all ADC building blocks along with their non-ideal effects have been implemented in MATLAB SIMULINK environment and the main transistor level circuits have been implemented in H-SPICE environment using 180-nm TSMC CMOS technology. The maximum DNL and INL amounts are equal to ±0.9 LSB and ±2.3 LSB, respectively. Applying a 33.1 MHz with 1.4 Vp-p (−6dBFS) input signal, achieved SNDR is 61 dB resulting in 9.8 Bits ENOB with total power consumption of 42 mW.