کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
6879463 | 1443114 | 2018 | 17 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
A fully integrated RSSI and an ultra-low power SAR ADC for 5.8â¯GHz DSRC ETC transceiver
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کلمات کلیدی
موضوعات مرتبط
مهندسی و علوم پایه
مهندسی کامپیوتر
شبکه های کامپیوتری و ارتباطات
پیش نمایش صفحه اول مقاله
![عکس صفحه اول مقاله: A fully integrated RSSI and an ultra-low power SAR ADC for 5.8â¯GHz DSRC ETC transceiver A fully integrated RSSI and an ultra-low power SAR ADC for 5.8â¯GHz DSRC ETC transceiver](/preview/png/6879463.png)
چکیده انگلیسی
This study presents a monolithic received signal strength indicator (RSSI) and an ultra-low power SAR ADC for 5.8â¯GHz DSRC transceiver in China electronic toll collection systems. In order to meet the stringent requirement of wide input range for the transceiver, two RSSIs collaborate with auxiliary ADC circuits to provide the digitalized received signal strength to the digital baseband of a transceiver. The RSSI design achieves fast transient response and low power consumption with a small die area by using internal active low-pass filters instead of external passive ones. The proposed design has been fabricated using a 0.13â¯Âµm 2P6M CMOS technology. Measurement results show that the overall input dynamic range is 86â¯dB with an accuracy of â¯Â±1.72â¯dB and a transient response of less than 2â¯Âµs. Compared with the state-of-the-art designs in the literature, the overall input range and transient settling time are improved by at least 14.6%, and 300%, respectively.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: AEU - International Journal of Electronics and Communications - Volume 86, March 2018, Pages 154-163
Journal: AEU - International Journal of Electronics and Communications - Volume 86, March 2018, Pages 154-163
نویسندگان
Meijuan Zhang, Ruifeng Liu, Yuanzhi Zhang, Wenshen Wang, Huimin Liu, Chao Lu,