Implementation of memory-efficient linear pipelined IPv6 lookup and its significance in smart cities

The recent trend towards IPv6 (Internet protocol version 6) has gained a great deal of interest with regard to smart cities due to its increased address space. A vital issue in designing a router is to establish the output port of an incoming IP packet along with its destination. Thus, the IP lookup architecture must achieve high speeds, supporting IPv6 with quick real-time updates to serve perpetually developing routing tables. The problem with IP lookup is that of achieving a throughput of more than 100 gigabits per second. In addition, it is difficult to store all the IP lookups in the on-chip memory devices. This paper proposes a new pipeline design called the linear pipelined IPv6 lookup architecture that overcomes the shortcomings of the POLP (parallel optimized linear pipeline) and BPFL (balanced parallelized frugal lookup) algorithms. The new B-tree algorithm is based on the idea of specific prefixes along with robust routing tables. The linear pipelined IP lookup design has been implemented in Verilog HDL using an Altera Quartus Stratix II device. Three different sizes of lookup tables are utilized to assess the proposed method. The logic elements, SRAM, memory and maximum frequency results are better for the proposed method compared with the POLP and BPFL methods.