VLSI architecture for fixed mesh based deformable motion estimation using ARPS algorithm

This paper proposes an architecture for fixed mesh based deformable motion estimation block of video encoder. While block motion estimation assumes purely translational motion in the video, the mesh based technique models non-translational motion as well. ASIC implementation of the proposed architecture (without decimation filter) using Synopsys tool (0.18 µm) at 100 MHz consumes 4.89 mW and occupies 0.076 mm2. It has achieved maximum frequency of 344.8 MHz with patch size of 16 and can process 613 frames of slow and 249 frames of fast motion CIF format video per second. Thus, the proposed architecture fits well for applications like video surveillance and video conferencing.