High-performance dynamic elastic pipelines

In this paper, we will propose a new class of synchronous elastic pipelines called Dynamic Elastic Pipeline (DELP) that employs dynamic logic family and achieves improved throughput and elasticity. Since these pipelines are synchronous, they can be supported by Electronic Design Automation (EDA) flows, and as they are elastic, they benefit from elasticity of asynchronous circuits. In synchronous elastic circuits, elasticity is like that they are able to stretch or shrink the clock's pulses with a constant step. PS0 style, as well as conventional synchronous Static ELastic Pipeline (SELP) are used as the reference point, yet achieve remarkable improvements through novel control circuit optimizations. This paper concentrates on designing very fine-grain or gate-level pipelines in which the datapath is partitioned into stages with only a single level depth logic. Two new single-rail and dual-rail pipelines have been implemented and all implementations have been characterized by low-cost control structures and latchless design. Post-layout simulations in 90 nm technology reveal that the proposed dual-rail DELP design has 19.1% higher throughput than that of Williams' PS0. Also, comparing to the synchronous SELP, our novel single-rail DELP achieves 52.4% higher throughput.