کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
6893671 | 1445568 | 2018 | 6 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
Decimal multiplication using compressor based-BCD to binary converter
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کلمات کلیدی
موضوعات مرتبط
مهندسی و علوم پایه
مهندسی کامپیوتر
علوم کامپیوتر (عمومی)
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چکیده انگلیسی
The objective of this work is to implement a scalable decimal to binary converter from 8 to 64â¯bits (i.e 2-digit to 16-digit) using parallel architecture. The proposed converters, along with binary coded decimal (BCD) adder and binary to BCD converters, are used in parallel implementation of Urdhva Triyakbhyam (UT)-based 32-bit BCD multiplier. To increase the performance, compressor circuits were used in converters and multiplier. The designed hardware circuits were verified by behavioural and post layout simulations. The implementation was carried out using Virtex-6 Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) with 90-nm technology library platforms. The results on FPGA shows that compressor based converters and multipliers produced less amount of propagation delay with a slight increase of hardware resources. In case of ASIC implementation, a compressor based converter delay is equivalent to conventional converter with a slight increase of gate count. However, the reduction of delay is evident in case of compressor based multiplier.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Engineering Science and Technology, an International Journal - Volume 21, Issue 1, February 2018, Pages 1-6
Journal: Engineering Science and Technology, an International Journal - Volume 21, Issue 1, February 2018, Pages 1-6
نویسندگان
Sasidhar Mukkamala, Pradeep Rathore, Rangababu Peesapati,