کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
6893794 | 1445570 | 2017 | 6 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
Vedic algorithm for cubic computation and VLSI implementation
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کلمات کلیدی
موضوعات مرتبط
مهندسی و علوم پایه
مهندسی کامپیوتر
علوم کامپیوتر (عمومی)
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چکیده انگلیسی
Algorithm of cubic computation and its VLSI implementation is described in this paper through 'Vedic mathematics' formulae. An N-bit cubic implementation circuit was structured into two cubic subgroups (bit length = N2 or lesser), multiplier and adder. VLSI aspects such as propagation delay and dynamic power consumption of such circuitry were lessened down notably by reducing the number of partial products. Designs implementation and estimation of performance parameters: delay and power consumption were figured out by spice spectre with 90 nm CMOS technology. The estimated values for propagation delay and power consumption of the reported 8-bit cubic circuitry were â¼5.5 ns and â¼2.6 mW respectively. Propagation delay has been enhanced by â¼12% and power consumption dropped down by â¼22% in comparison to its counterpart (traditional architecture).
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Engineering Science and Technology, an International Journal - Volume 20, Issue 5, October 2017, Pages 1494-1499
Journal: Engineering Science and Technology, an International Journal - Volume 20, Issue 5, October 2017, Pages 1494-1499
نویسندگان
Deepak Kumar, Prabir Saha, Anup Dandapat,