کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
6894000 | 1445574 | 2017 | 6 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
Layout parameter analysis in Shannon expansion theorem based on 32Â bit adder circuit
دانلود مقاله + سفارش ترجمه
دانلود مقاله ISI انگلیسی
رایگان برای ایرانیان
کلمات کلیدی
موضوعات مرتبط
مهندسی و علوم پایه
مهندسی کامپیوتر
علوم کامپیوتر (عمومی)
پیش نمایش صفحه اول مقاله

چکیده انگلیسی
The 1-bit adder circuits are schematized using pass transistor logic (PTL) technique, that's optimized by the Shannon expansion theorem. The proposed 32Â bit carry increment adder (CIA) circuit is designed by bit slice method. The CIA adder layout gives tremendous change compared to existing author results. The proposed circuit achieved better performance on power consumption, speed, throughput, and area. The 32-bit adder circuits are implemented in various types of 1-bit adder cells, such as Shannon, Mixed-Shannon and MCIT-7T. Furthermore, the 32-bit CIA adder layout is furtherly investigated for RLC interconnect parameter such as capacitive impedance, inductive impedance, power factor sin Ï, tan Ï for applying frequency. The 32Â bit adder circuit acts in a better way than existing circuits in terms of power dissipation, delay, throughput, latency, power factor, sin Ï and tan Ï.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Engineering Science and Technology, an International Journal - Volume 20, Issue 1, February 2017, Pages 35-40
Journal: Engineering Science and Technology, an International Journal - Volume 20, Issue 1, February 2017, Pages 35-40
نویسندگان
C. Senthilpari, K. Diwakar, Kumar Munusamy, J. Sheela Francisca,