کد مقاله کد نشریه سال انتشار مقاله انگلیسی نسخه تمام متن
6894000 1445574 2017 6 صفحه PDF دانلود رایگان
عنوان انگلیسی مقاله ISI
Layout parameter analysis in Shannon expansion theorem based on 32 bit adder circuit
کلمات کلیدی
موضوعات مرتبط
مهندسی و علوم پایه مهندسی کامپیوتر علوم کامپیوتر (عمومی)
پیش نمایش صفحه اول مقاله
Layout parameter analysis in Shannon expansion theorem based on 32 bit adder circuit
چکیده انگلیسی
The 1-bit adder circuits are schematized using pass transistor logic (PTL) technique, that's optimized by the Shannon expansion theorem. The proposed 32 bit carry increment adder (CIA) circuit is designed by bit slice method. The CIA adder layout gives tremendous change compared to existing author results. The proposed circuit achieved better performance on power consumption, speed, throughput, and area. The 32-bit adder circuits are implemented in various types of 1-bit adder cells, such as Shannon, Mixed-Shannon and MCIT-7T. Furthermore, the 32-bit CIA adder layout is furtherly investigated for RLC interconnect parameter such as capacitive impedance, inductive impedance, power factor sin ϕ, tan ϕ for applying frequency. The 32 bit adder circuit acts in a better way than existing circuits in terms of power dissipation, delay, throughput, latency, power factor, sin ϕ and tan ϕ.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Engineering Science and Technology, an International Journal - Volume 20, Issue 1, February 2017, Pages 35-40
نویسندگان
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