Comparative analysis of adiabatic full adder cells in CNFET technology

The advent and widespread use of portable devices and their large market share have turned the spotlight on low-power design of such battery-operated systems. Arithmetic unit is the heart of a media processor embedded in portable electronic devices. Therefore, a low-power implementation of full adder cell, which is the basic building block of arithmetic structures, may significantly reduce the whole power of the mentioned systems. One of the well-known methods for reducing power dissipation in systems with high switching activity is the adiabatic logic. Due to the problems of the MOS scaling, carbon nanotube field effect transistor (CNFET) has been introduced as the most promising replacement for today's FET devices. In this paper, various hybrid topologies of full adder cell are reviewed and implement based on the adiabatic logic with reduced transistor count. The simulations are conducted under various conditions such as different operating frequencies, load capacitors and supply voltages that may occur in realistic conditions. Moreover, ripple carry adder is realized in both adiabatic and non-adiabatic families in order to carry out more comprehensive analyses. Finally, regarding the fact that integrated circuits in Nano regime are much more sensitive to process variations, the robustness of such circuits against these variations is surveyed and analyzed.