BIST Architecture for Multiple RAMs in SoC

Testing of Memory cores has an important role in the process of testing System-on-Chip (SoC) for detecting faults and improving overall yield and quality. Most common method used for testing embedded circuits automatically is the Built-in self-test method. BIST is superior to other existing methods as it decreases the test time at the cost of area. The test time can be reduced further if the testing is done in parallel mode. This paper suggests a method for testing multiple Memory cores in parallel. As more fault coverage is offered by March tests, it is also incorporated for the test.