Modeling of the CPU frequency to minimize energy consumption in parallel applications

Although high-performance computing traditionally focuses on the efficient execution of large-scale applications, power consumption is going to become a critical design constraint for exascale systems. Drastic increases in the power consumption of supercomputers affect significantly their operating costs and failure rates. In modern microprocessor architectures, equipped with dynamic voltage and frequency scaling (DVFS) and CPU clock modulation (throttling), the power consumption may be controlled in software. Additionally, network interconnect, such as Infiniband, may be exploited to maximize energy savings while the application performance loss and frequency switching overheads must be carefully balanced. This work proposes a model for determining a frequency level that minimizes energy consumption during parallel application execution. This model features a closed-form expression for the optimal frequency with respect to several application and system parameters. The model is then validated on the entire original suite of the NAS parallel benchmarks, thereby being exposed to different types of workloads. The obtained closed-form expression provides insights into the viability of energy consumption with changes in processor frequency and clearly shows that a simplistic strategy of just lowering the operating frequency does not always yield a reduced energy consumption. Average energy savings of 7% have been achieved by using the optimal frequency determined by the proposed model for the NAS benchmarks.