P2NoC: Power- and Performance-aware NoC Architectures for Sustainable Computing

Communication performance over distant nodes and high power consumption are major challenges for efficient Network-on-Chip (NoC) architectures. Wireless NoCs, by augmenting wired topologies with low latency wireless links, overcome performance limitations of conventional NoCs. However, NoC routers and Wireless Interfaces (WIs) consume significant amount of leakage power. The usage of routers in NoC is application dependent and for most applications, performance requirement can be achieved without operating all resources all the time. Similarly, WIs transmitting data over shared channel can be selectively turned off when they are not active. Exploiting these, we propose Power- and Performance-aware NoC (P2NoC) architecture that power gates router elements and WIs depending upon their utilization to reduce leakage power. P2NoC works based on hybrid two-level router utilization estimate; pre-computed and runtime to provide coarse and fine estimate of utilization to maximize power saving while keeping overheads and performance impact to a minimum. We also propose deadlock-free seamless bypass routing strategy with P2NoC to avoid adverse impacts of power gating. P2NoC saves up to 92.20% and 68.23% of leakage power in base and hybrid routers respectively with only 7% area overhead. Based on utilization, P2NoC also reduces total average packet energy consumption by 49% with negligible performance degradation. The proposed solution provides a flexible sustainable computing platform that can be optimized for a wide range of application scenarios.