Logic Synthesis for FPGAs of Interpreted Petri Net with Common Operation Memory*

The method of synthesis of the logic circuit of interpreted Petri net is proposed in this paper. Proposed method is based on the minimal encoding of places. Places are encoded in subsets. Each subset is represented by one color of colored Petri net. Operations assigned to places are placed in memory. It leads to realization of logic circuit in two-level architecture, where the combinational circuit of first level is responsible for firing transitions and the second level memory is responsible for the generation of operations. Such approach allows balanced usage of different kinds of resources available in modern FPGAs.