I2C Interface Design for Hardware Master Devices

In the paper, we present the design of I2C compatible interface for hardware master devices that outputs data irregularly in time. The corresponding interface was implemented by developing the relevant VHDL code and a synthesis into standard VLSI cells. The interface operation was validated by tests using the ActiveHDL simulator. Furthermore, the evaluation of power consumption of the interface chip obtained on the basis of Cadence SoC Encounter System is reported.