On Mapping of DSP48 Units for Arithmetic Operation in Reconfigurable Logic Controllers

The paper presents a case study of arithmetic operation mapping to DSP48 units. It is a part of developed toolset for arithmetic operation synthesis dedicated to reconfigurable logic controllers programmed according to IEC1131 and EN61131. The program is compiled to hardware structure with a massive parallel processing. The developed method automatically allocates resources and maps operations to DSP48 units and necessary additional components required for other operations and data flow maintenance. It controls resource usage and operation timing. Using scheduling methodology allow to reduce execution cycles and properly utilize available components. The system apart from operation mapping generates control unit for data flow maintenance making complete solution for arithmetic implementation. Finally an example of PID controller implementation is considered. Introducing the automatic implementation method allows flexible implementing the control algorithms. The maximal possible parallelism (limited only by the algorithm dependencies and available resources) is introduced.