Implementation of Massive Artificial Neural Networks with Field-programmable Gate Arrays

This paper presents a novel method for implementing massive artificial neural networks (ANN) with field-programmable gate arrays (FPGA). Because of the sequential nature of programs, the execution of large ANNs in software is inefficient. On the other hand, in FPGA devices that consist of a large number of programmable circuits, the nodes of ANN may be executed in parallel. This provides for higher computational rates and a greater degree of robustness or fault tolerance than in conventional computers. The main goal of these studies was to implement as many neurons as possible on a single FPGA device, without giving up the minimal execution times. In the proposed solution, each neuron is implemented by a single multiplier. For the nonlinear behaviour of a neuron, the activation function is approximated using several linear segments. In order to overcome the limited memory capacity of FPGA, external memory is employed Execution of ANN is controlled by an embedded soft processor.