Control Induced Explicit Time-Scale Separation to Attain DC Voltage Stability for a VSC-HVDC Terminal

This paper proposes a novel control scheme to regulate the DC voltage of a VSC terminal. It significantly simplifies the control design process itself and also results in an uncomplicated and efficient control architecture. First, we present an equivalent state-space model established in a synchronous dq reference frame. Subsequently, we split the overall system into two interconnected subsystems and suppose that they have different dynamics. Based on this assumption, a reduced model is derived by using singular perturbation techniques. The developed control structure is actually based on this reduced model and an explicit time-scale separation. Simulation results clearly demonstrate that the proposed control strategy can regulate the DC voltage with good performances. Moreover, the real DC voltage can be well approximated by the solution of the reduced model.