High resolution shallow vertical Hall sensor operated with four-phase bi-current spinning current

Vertical Hall-effect devices (VHDs) are CMOS integrated sensors dedicated to the measurement of magnetic field in the plane of the chip. At low frequency, their performances are severely reduced by 1/f noise. This paper presents the capability of a bi-current biasing combined to a four-phase spinning current technique (SCT) to lower 1/f noise and improve the resolution of shallow VHD designed in low-voltage CMOS technologies (LV-VHD). It has been shown that applying the highest achievable biasing current on each phase of the SCT and combining it with a switched gain, the sensor resolution can be optimized. A practical way to implement this technique is proposed, and experiments obtained from a 3 μm wide, 25 μm long LV-VHD integrated in the AMS 0.35 μm CMOS technology show that 1/f noise is efficiently reduced, leading to a resolution of 51 μT over a 1.6 kHz bandwidth with an average biasing current of only 825 μA.