Generating time intervals in Programmable Logic Controllers

The paper presents a review of methods of implementing timers in Programmable Logic Controllers, along with a discussion of the timer properties. The authors focus on software implementations, as this approach has dominated practical solutions. An important part of the discussion is analysis of errors in time delay generation, and possible error sources. A typical case of a PLC generating a predefined time delay is analyzed. The discussion is concluded with recommendations on implementing timers, intended for PLC designers.