Banyan Switch Applied for LDPC Decoder FPGA Implementation

Low-Density Parity-Check codes are one of the best modern error-correcting codes due to their excellent error-correcting performance and highly parallel decoding scheme. This article concerns the hardware iterative decoder for a subclass of LDPC codes that are implementation oriented, known also as Architecture Aware LDPC. The parameterizable decoder has been designed in the form of synthesizable VHDL description. Implementation in Xilinx FPGA devices achieves throughput nearly 100Mb/s. Significant part of the decoder area is occupied by Configurable Interconnection Network. The network consists of a set of multiplexers that propagate the data from memory to the computation units. Behavioral description of the interconnection network gives quite poor synthesis results: decoder area is large and exponentially dependent on the number of inputs / outputs. Instead of straightforward behavioral description, the switching network can be described structurally making use of ideas known from theory of telecommunication interconnection networks: Benes or Banyan switches. In this article 1 present in detail the interconnection network implementation based on Banyan switch with additional multiplexer stage to enable non-power-of-2 numbers of outputs. Comparison of synthesis results for the network obtained by synthesis of behavioral description as well as the Banyan structural description shows significant decrease of decoder area in the second case.