Dynamic partial reconfiguration of CPU-s for Programmable Logic Controllers executing control programs developed in the Ladder Diagram language

The paper presents a method for hierarchical description of control algorithms with their partitioning into tasks that are executed sequentially and those that run concurrently. The proposed method is based entirely on components available in the Ladder Diagram (LAD) language, and can be considered as an alternative to the Sequential Function Chart (SFC) diagrams. In addition, an architecture for a reconfigurable logic controller is proposed, which is capable of executing the control program combined hardware and software tasks. For that purpose the mechanism of dynamic partial reconfiguration of programmable gate arrays (FPGA-s) is used. This makes possible to download to the programmable structure only those tasks, which are currently required by the running control algorithm. Such a hardware implementation of the controller enables effective execution of concurrent control tasks by parallel operation of the control processing units. Finally, a proposed controller architecture allows using a programmable device of a reduced size, and this makes the solution more cost-effective.