Firmware Optimization for Embedded Logic Control

This paper presents a new method to represent a subclass of multiple-output incompletely specified functions by means of multi-terminal binary decision diagrams (MTBDDs). Algorithm to reduce the cost and width of MTBDDs is presented. A software CAD tool makes use of iterative decomposition to obtain a MTBDD data structure that can be directly mapped to firmware in a form of chained dispatch tables. A practical example shows that there is a space-time trade-off between the amount of memory required for all dispatch tables in a control store and the speed of firmware execution. Support for multi-way branching in a micro-sequencer is assumed.