Performance Analysis of Reconfigurable Clusters to Design Good Error Correcting Codes in Communications

In this paper we present a study where parallel computers and FPGA devices arranged in a cluster way are compared when running an application of the evolutionary computing. The motivation of the work is to demonstrate how reconfigurable hardware takes advantage in large optimization problems tackled with evolutionary algorithms when the arithmetic operations are massively parallelized. For this purpose, we have chosen the error correcting codes optimization problem, a problem existing in the communication systems. The binary linear block codes detects and/or corrects the errors occurred during the data transmission. The problem to find a code that corrects a maximum number of errors is a NP-complete optimization problem, being this a problem suitable for massive parallel computations. After designing the system and implementing it on several reconfigurable devices, we show the performance results that improves the corresponding ones to general purpose processors.