Multi-Level Implementation of Asynchronous Logic Using Two-Level Nodes

A novel synthesis method of a dual-rail asynchronous multi-level logic is proposed. The logic is implemented as a monotonous multi-level network of minimized AND-OR nodes together with the completion detection logic. Each node is a hazard-free structure. It is achieved based on the product term minimization constraint that the authors have formulated and proved in their previous paper. The MCNC and ISCAS benchmark sets were processed and the area overhead with respect to the synchronous implementation was evaluated. Then the implementation complexity of the proposed method and a state-of-the-art method based on the duplication of every gate was compared. A considerable improvement was obtained.