Design of Reconfigurable Logic Controllers from Petri Net-based specifications

The paper promotes to construct a synthesizable VHDL model from a graphical representation of Petri Net. The VHDL code provides a clear semantics of graphically designed reconfigurable logic controller and serves as reference model for eventual further optimization efforts. It is considered that automatically generated array structure of logic controller is optimized for synthesis by professional tools. The most useful aspect for presented purposes is the ability to execute a VHDL behavioral specification closely related with array-based implementation. Even if the final implementation is not optimized during the logic synthesis process, it is compact, easy to modify and efficient.