HEDEFS – HARDWARE EMBEDDED DEDUCTIVE FAULT SIMULATION

Hardware Embedded DEductive Fault Simulation (HEDEFS) is a hardware-software realization of a deductively-parallel topological method of faults modeling. The method uses ad hoc technology of the analysis of converging branching, back-word modeling of faults simulation, and transformation of testable circuits; and is oriented on handling of digital circuits with big dimension represented on gate or RT description levels. Structural hardware solutions for realization of the method are presented at an estimation of quality of generated tests.