STATISTICAL DETECTION OF THE FAULTY BEHAVIOUR OF ISLIP-BASED SCHEDULERS FOR VOQ SWITCHES

High-speed telecommunications routers are very important systems in today's networked environments. In order to improve their quality of service, it is important to provide them with means to detect errors that affect their behaviour. If such detection is performed concurrently with normal operation, the negative effects of errors could be mitigated or even avoided, leading to fault-tolerant operation. This work concentrates on the scheduler part of the system and, in particular, on concurrent error detection in circuits implementing the well-known iSLIP scheduling algorithm. The faulty behaviour of complex digital processing systems is usually better described at the algorithmic level, particularly when the operation of the system relies on complex mathematical principles. Therefore, the issues related to concurrent error detection are addressed from a mathematical model of the target system. Results are presented that point to the ability of the proposed solution to detect errors at a high abstraction level.