ARBITRATION CIRCUIT WITH CYCLICALLY SHIFTED PRIORITIES FOR MULTIPROCESSOR SYSTEM

The paper presents the arbitration circuit that was designed for a classical multiprocessor system with a common memory and a time-sharing bus. The arbitration algorithm called “with cyclically shifted priorities” was implemented in this arbiter. The arbitration circuit was designed as modular and expandable. Thanks to proper hardware solutions the arbiter has a simply logic structure. This logic structure was implemented in FPGA. Operation of the arbiter in the real multiprocessor system was described. Block diagrams of all parts of this arbitration circuit were shown. A queueing model of the multiprocessor system with the arbiter was presented. Thanks to this, it was possible to predict performance of this system. The method of performance calculation of the multiprocessor system with the presented arbitration circuit was described. The analytic results were compared with the corresponding measured results that were obtained in the real multiprocessor system. The analytic and measured results were shown in a graphic form in figures.