ESD design automation & methodology to prevent CDM failures in 130 & 90 nm ASIC design systems

Design automation tools for ESD are described that ensure robust protection at both the cell and chip level in a high-volume, highly automated ASIC design system. The Charged Device Model (CDM) failure modes discovered in the 130 nm technology are described, and the design automation tools that were implemented to prevent these failures are presented. There are three primary components: Design rule checking for ESD; transient CDM simulations on extracted net lists; and analysis of chip-level power supply net resistances.