Application specific router architectures for NoCs: An efficiency and power consumption analysis

Networks on chip (NoC) have been proposed as a solution to mitigate complex on-chip communication problems. NoCs are composed of intellectual properties (IP) which are interconnected by on-chip switching fabrics. A step in the design process of NoCs is hardware virtualization which is mapping the IP cores onto the tiles of a chip. The communication among the IP cores greatly affects the performance and power consumption of NoCs which itself is deeply related to the placement of IPs onto the tiles of the network. Different mapping algorithms have been proposed for NoCs which allocate a set of IPs to given network topologies. In these mapping algorithms, there is a restriction which limits IPs to be mapped only onto single routers. This, results in heavy traffic loads on routers connected to high communicating processing cores. In order to increase the performance of the NoCs and decrease their energy consumption, a new mapping method is proposed here that makes efficient use of the network area and its components. This new mapping methodology and placement aims to assign a proper number of routers to IP(s) implemented inside a chip to maximize performance and minimize power consumption. The mapping algorithm attaches more than one processing core onto routers where ever the communication process is less than computation.