Intrinsic limits of the sensitivity of CMOS integrated vertical Hall devices

Current researches on CMOS integrated Hall devices focus on the vertical Hall device (VHD) since this structure limits the performances of monolithic three-dimensional Hall probes. The well known conventional horizontal Hall device (HHD) has probably been brought closed to its optimal performances while integrated in CMOS technologies. On the contrary, the VHD which is more complex to study theoretically still asks for a better understanding in order to improve its performances that are lower than those of a HHD as it was demonstrated experimentally in many previous works. The aim of this paper is to discuss this experimentally observed difference between VHD and HHD through an analysis of 2D FEM calculations. Especially, we explain why the conventional VHD with two sensing contacts exhibits an intrinsic lower sensitivity. This lower sensitivity is responsible for the lower signal to noise ratio and the higher offset. We also introduce coefficients which allow to determine the sensitivity of a VHD depending on its geometry. Finally we explain why a measurement of the Hall voltage through four sensing contacts instead of two is mandatory to reach the maximum sensitivity.