Measurements of thermoelectric properties of silicon pillars

Nanostructured silicon as a material for thermoelectrics provides several advantages over conventional materials, such as bismuth telluride or lead telluride. The technological processing of silicon is well advanced due to the rapid development of microelectronics in recent decades. Silicon is largely available and environmentally friendly. The operating temperature of silicon thermoelectric generators is higher (>250 °C) compared to bismuth telluride. So far silicon is rarely used as a thermoelectric material because of its high thermal conductivity. The figure of merit Z, which is the commonly used measure of the thermoelectric properties of materials, is thereby too small for device applications. In order to introduce silicon as an efficient thermoelectric material thermal conductivity has to be drastically reduced. Nanostructuring into wires, i.e. restriction of the device geometry in both dimensions perpendicular to the heat propagation path indicates a route towards lower thermal conductivity. In this study we investigated silicon pillars produced in a wafer-scale top-down process by ICP (Inductive Coupled Plasma) cryogenic dry etching followed by thermal oxidation and oxide stripping. The pillars have diameters from 2 μm down to 170 nm. Their heights vary from 26.7 μm to 32.1 μm. We measured the reduction of thermal conductivity due to decreasing of pillar diameter. 3ω measurements were performed using a Wollaston probe with pillars of diameters down to 700 nm showing a reduction of thermal conductivity of 27% compared to bulk silicon.