IEEE 1451.0 standard based smart readout for multi-rate control of system

This paper presents a novel architecture for multi-rate control system with disturbance estimation and rejection using FPGA connected with sensors and actuators through IEEE 1451 standard. A signum function is used for estimation error correction. Estimated states are used to provide the control input at a rate higher or lower than the sample rate thus providing multi-rate control. An architecture is proposed to implement the proposed multi-rate controller in FPGA platform through IEEE 1451.0-2007 standard. The control scheme requires minimum analog hardware, namely comparator and digital to analog convertor and provides multi-bit resolution with multi-rate processing.