Investigation of the chip to photodetector coupler with subwavelength grating on SOI

• Two kinds of investigation of the chip to photodetector coupler are designed.
• The coupler formed by an array of rectangular holes.
• The power absorption losses of uniform and blazed SWGs reach 73% and 75%.
• FDTD and BPM simulations are used to optimize the coupler design.
• The SWG was fabricated in the institute of microelectronics.

We report on two kinds of investigation of the chip to photodetector coupler (CTPC) with uniform and blazed subwavelength grating (SWG) on silicon-on-insulator (SOI) that were conducted for silicon-based hybrid photodetector integration in an arrayed waveguide grating demodulation integrated microsystem. The theoretical model is presented, 3D FDTD and BPM simulations are used to optimize the coupler design. InP/InGaAs photodetector and SOI wafer were integrated through benzocyclobutene bonding. An efficient high-power absorption for TE mode in a broad band is achieved. The power absorption efficiencies of uniform and blazed SWGs in silicon-based hybrid photodetector integration at 1550 nm reach 73% and 75%, respectively in the simulation and it reaches as high as 25% in the measurement when coupling the TE-polarized 1550 nm light.