Design and implementation of a capacitive fingerprint sensor circuit in CMOS technology

An ASIC implementation of capacitive fingerprint sensor is described for user authentication on small, thin, and portable equipment. New charge sharing sensing circuit minimizes the influence of internal parasitic capacitances and enlarges the voltage difference between a ridge and valley. A voltage comparator can easily discriminate a ridge and valley. Our method results in about 180% improvement in the voltage difference between a ridge and valley. The sensing circuit also includes a pixel-level automatic calibration scheme. The proposed calibration scheme initializes a capacitive fingerprint sensor LSI to eliminate the influence of the surface condition and environment, which is degraded by dirt during long-time use. The test chip is fabricated on a 0.35 μm standard CMOS 1-poly 4-metal process.