Whole-Chip ESD Protection Design for RF and AMS ICs

As integrated circuits (IC) technologies advance into very-deep-sub-micron (VDSM), electrostatic discharge (ESD) failure becomes one of the most devastating IC reliability problems and on-chip ESD protection design emerges as a major challenge to radio frequency (RF), analog, and mixed-signal (AMS) IC designs. This paper reviews key design aspects and recent advances in whole-chip ESD protection designs for RF/AMS IC applications in CMOS technologies.